Series resistance reduction in vertically stacked silicon nanowire transistors

ABSTRACT

Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

DOMESTIC PRIORITY

The present application claims priority to U.S. patent application Ser. No. 14/739,543 filed Jun. 15, 2015, titled “Series Resistance Reduction In Vertically Stacked Silicon Nanowire Transistors,” assigned to the assignee hereof and expressly incorporated by reference herein.

BACKGROUND

The present disclosure relates in general to semiconductor devices and their manufacture. More specifically, the present disclosure relates to the fabrication of vertically stacked nanowire transistors having improved source to drain sheet resistance.

Transistors are semiconductor devices commonly found in a wide variety of integrated circuits. A transistor is essentially a switch. When a voltage is applied to a gate of the transistor that is greater than a threshold voltage, the switch is turned on, and current flows through the transistor. When the voltage at the gate is less than the threshold voltage, the switch is off, and current does not flow through the transistor.

Typical semiconductor devices are formed using active regions of a wafer. The active regions are defined by isolation regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an integrated circuit having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. Complementary metal oxide semiconductor (CMOS) is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions.

Gate-all-around (GAA) nanowire channel field-effect transistors (FETs) enable feature scaling beyond current planar CMOS technology. In its basic form, a nanowire-based FET includes a source region, a drain region and stacked nanowire channels between the source and drain regions. A gate which surrounds the stacked nanowire channels regulates electron flow through the nanowire channels between the source and drain regions. Forming GAA nanowires from alternating epitaxial layers of nanowire silicon (Si) and sacrificial silicon germanium (SiGe) provides superior channel electrostatics control, which is necessary for continuously scaling gate lengths down to seven (7) nanometer technology and below. However, the inclusion of stacked, strained Si/SiGe nanowire/sacrificial layers in the channel region of a GAA nanowire FET structure makes junction design and extension series resistance (R_(ext)) reduction difficult. A reduction in R_(ext) would lead to enhanced driver current performance.

SUMMARY

Embodiments are directed to a method of fabricating a portion of a nanowire FET. The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

Embodiments are further directed to a nanowire FET including a sacrificial layer, a nanowire layer and a diffusion block formed adjacent to the sacrificial layer. The nanowire FET further includes a source region and a drain region positioned such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, wherein the diffusion block prevents a sacrificial layer removal process performed during fabrication of the nanowire FET from also removing portions of at least one of the source region and the drain region.

Additional features and advantages are realized through techniques described herein. Other embodiments and aspects are described in detail herein. For a better understanding, refer to the description and to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as embodiments is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1A depicts a perspective view of a semiconductor device after a fabrication stage according to one or more embodiments;

FIG. 1B depicts a cross-sectional view of the semiconductor device shown in FIG. 1A, taken along line 1B-1B;

FIG. 1C depicts a cross-sectional view of the semiconductor device shown in FIG. 1A, taken along line 1C-1C;

FIG. 2A depicts a perspective view of a semiconductor device after a fabrication stage according to one or more embodiments;

FIG. 2B depicts a cross-sectional view of the semiconductor device shown in FIG. 2A, taken along line 2B-2B;

FIG. 2C depicts a cross-sectional view of the semiconductor device shown in FIG. 2A, taken along line 2C-2C;

FIG. 3A depicts a perspective view of a semiconductor device after a fabrication stage according to one or more embodiments;

FIG. 3B depicts a cross-sectional view of the semiconductor device shown in FIG. 3A, taken along line 3B-3B;

FIG. 3C depicts a cross-sectional view of the semiconductor device shown in FIG. 3A, taken along line 3C-3C;

FIG. 4A depicts a perspective view of a semiconductor device after a fabrication stage according to one or more embodiments;

FIG. 4B depicts a cross-sectional view of the semiconductor device shown in FIG. 4A, taken along line 4B-4B;

FIG. 4C depicts a cross-sectional view of the semiconductor device shown in FIG. 4A, taken along line 4C-4C;

FIG. 5A depicts a perspective view of a semiconductor device after a fabrication stage according to one or more embodiments;

FIG. 5B depicts a cross-sectional view of the semiconductor device shown in FIG. 5A, taken along line 5B-5B;

FIG. 5C depicts a cross-sectional view of the semiconductor device shown in FIG. 5A, taken along line 5C-5C;

FIG. 6A depicts a perspective view of a semiconductor device after a fabrication stage according to one or more embodiments;

FIG. 6B depicts a cross-sectional view of the semiconductor device shown in FIG. 6A, taken along line 6B-6B;

FIG. 6C depicts a cross-sectional view of the semiconductor device shown in FIG. 6A, taken along line 6C-6C;

FIG. 7A depicts a perspective view of a semiconductor device after a fabrication stage according to one or more embodiments;

FIG. 7B depicts a cross-sectional view of the semiconductor device shown in FIG. 7A, taken along line 7B-7B;

FIG. 7C depicts a cross-sectional view of the semiconductor device shown in FIG. 7A, taken along line 7C-7C;

FIG. 8A depicts a perspective view of a semiconductor device after a fabrication stage according to one or more embodiments;

FIG. 8B depicts a cross-sectional view of the semiconductor device shown in FIG. 8A, taken along line 8B-8B;

FIG. 8C depicts a cross-sectional view of the semiconductor device shown in FIG. 8A, taken along line 8C-8C;

FIG. 9A depicts a perspective view of a semiconductor device after a fabrication stage according to one or more embodiments;

FIG. 9B depicts a cross-sectional view of the semiconductor device shown in FIG. 9A, taken along line 9B-9B;

FIG. 9C depicts a cross-sectional view of the semiconductor device shown in FIG. 9A, taken along line 9C-9C;

FIG. 10A depicts a perspective view of a semiconductor device after a fabrication stage according to one or more embodiments;

FIG. 10B depicts a cross-sectional view of the semiconductor device shown in FIG. 10A, taken along line 10B-10B;

FIG. 10C depicts a cross-sectional view of the semiconductor device shown in FIG. 10A, taken along line 10C-10C;

FIG. 11 depicts a cross-sectional view of the semiconductor device shown in FIG. 10A, taken along line 11-11;

FIG. 12 depicts a cross-sectional view of the semiconductor device shown in FIG. 11 after a fabrication stage according to one or more embodiments; and

FIG. 13 is a flow diagram illustrating a methodology according to one or more embodiments.

DETAILED DESCRIPTION

It is understood in advance that although this disclosure includes a detailed description of an exemplary GAA nanowire FET configuration, implementation of the teachings recited herein are not limited to a particular FET structure disclosed herein. Rather, embodiments of the present disclosure are capable of being implemented in conjunction with any other type of FET device now known or later developed.

A semiconductor structure may comprise a number of FETs, with each FET including a source, a drain, a channel and a gate. The channel connects the source and the drain, and electrical current flows through the channel from the source to the drain. The electrical current flow is induced in the channel by a voltage applied at the gate. The size of an FET is related to the electrical conductivity of the channel material. If the channel material has a relatively high conductivity, the FET may be made correspondingly smaller. In a relatively small FET, a channel may comprise a nanostructure, also referred to as a nanowire.

As previously noted herein, GAA nanowire channel FETs enable feature scaling beyond current planar CMOS technology. In its basic form, a nanowire-based FET includes a source region, a drain region and stacked nanowire channels between the source and drain regions. A gate which surrounds the stacked nanowire channels regulates electron flow through the nanowire channels between the source and drain regions. Forming GAA nanowires from alternating epitaxial layers of nanowire silicon (Si) and sacrificial silicon germanium (SiGe) provides superior channel electrostatics control, which is necessary for continuously scaling gate lengths down to seven (7) nanometer technology and below. The use of SiGe/Si sacrificial/nanowire layers to form the channel regions in semiconductor devices provides desirable device characteristics, including the introduction of strain at the interface between SiGe and Si. However, the inclusion of stacked, strained Si/SiGe nanowire/sacrificial layers in the channel region of a GAA nanowire FET structure makes junction design and R_(ext) reduction difficult. A reduction in R_(ext) would lead to enhanced driver current performance.

Accordingly, the present disclosure provides fabrication methodologies and resulting devices for stacked nanowire transistors having improved source to drain sheet resistance. In one or more embodiments, the semiconductor device fabrication methodology includes processes to remove and release sacrificial layers from nanowire layers that will form the channel region of the device. A diffusion block is locally formed between the sacrificial layers and the source and drain regions of the device. The diffusion block is positioned such that processes that remove the sacrificial layers of the channel region during device fabrication do not also attack the source and drain regions of the device. As described in greater detail herein below, the diffusion block may be formed from nitride, which prevents excess gauging during certain reactive ion etch (RIE) processes that may be applied during the sacrificial layer removal process of the overall device fabrication process. Although the diffusion block in the disclosed embodiments is formed from nitride, it may be formed from any material for which subsequent device fabrication operations are not very selective. Selectivity, as used in the present disclosure, refers to the tendency of a process operation to impact a particular material. One example of low selectivity is a relatively slow etch rate. One example of a higher or greater selectivity is a relatively faster etch rate. For the disclosed embodiments, a material for the diffusion block is selected based on a selectivity of subsequent device fabrication operations for the selected material being below a predetermined threshold.

FIGS. 1-12 are diagrams illustrating a GAA nanowire FET device at various stages of a fin-first, wire-last replacement gate fabrication methodology according to one or more embodiments of the present disclosure. As described in greater detail herein below, in accordance with one or more embodiments of the present disclosure, a diffusion block section is formed locally and positioned between a sacrificial layer of the nanowire FET device and the source and drain regions of the nanowire FET device. The diffusion block is positioned such that a process that removes the sacrificial layer during device fabrication does not also attack the source and drain regions of the nanowire FET device.

As shown in FIGS. 1A to 1C, an alternating series of nanowire Si layers and sacrificial SiGe layers are formed in a stack on a bulk Si substrate 102. Specifically, FIG. 1A depicts a three dimensional (perspective) illustration of a SiGe sacrificial layer 104 epitaxially grown on bulk Si substrate 102. FIG. 1B depicts a cross sectional view of the semiconductor device shown in FIG. 1A taken along line 1B-1B, and FIG. 1C depicts a cross sectional view of the semiconductor device shown in FIG. 1A taken along line 1C-1C. FIG. 2A depicts a three dimensional illustration of an undoped nanowire Si layer 202 epitaxially grown on sacrificial SiGe layer 104. FIG. 2B depicts a cross sectional view of the semiconductor device shown in FIG. 2A taken along line 1B-2B, and FIG. 2C depicts a cross sectional view of the semiconductor device shown in FIG. 2A taken along line 2C-2C. FIG. 3A depicts a three dimensional illustration of another sacrificial SiGe layer 302 epitaxially grown on nanowire Si layer 202. FIG. 3B depicts a cross sectional view of the semiconductor device shown in FIG. 3A taken along line 3B-3B, and FIG. 3C depicts a cross sectional view of the semiconductor device shown in FIG. 3A taken along line 3C-3C. FIG. 4A depicts a three dimensional illustration of an undoped nanowire Si layer 402 epitaxially grown on sacrificial SiGe layer 302. FIG. 4B depicts a cross sectional view of the semiconductor device shown in FIG. 4A taken along line 4B-4B, and FIG. 4C depicts a cross sectional view of the semiconductor device shown in FIG. 4A taken along line 4C-4C. For ease of illustration, four alternating layers 104, 202, 302, 402 are shown. However, one or more additional sacrificial layers and/or crystalline nanowire layers may optionally be epitaxially grown in an alternating fashion on top of substrate 102, wherein the properties of the additional sacrificial layer(s) are the same as sacrificial layers 104, 302, and the properties of the additional crystalline nanowire layer(s) are the same as nanowire Si layers 202, 402.

Known processing techniques are applied to the semiconductor device structure shown in FIGS. 4A-4C to form a plurality of fin-shaped regions 502, 504 having alternating layers of sacrificial SiGe 104, 302 and nanowire Si 202, 402, which are shown as a three dimensional view in FIG. 5A and two dimensional views in FIGS. 5B and 5C. For example, the known processing techniques may include the formation of fin hard masks (not shown) over nanowire Si layer 402. The fin hard masks may be formed by first depositing the hard mask material (for example silicon nitride) onto nanowire Si layer 402 using, for example, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) or any suitable technique for dielectric deposition that does not induce a physical or chemical change to nanowire Si layer 402. According to an exemplary embodiment, the hard mask material is deposited onto nanowire Si layer 402. The deposited hard mask material is then patterned into a plurality of the individual fin hard masks. The patterning of the hard masks is commensurate with a desired footprint and location of fin-shaped regions 502, 504, which will be used to form the channel regions of the semiconductor device. According to an exemplary embodiment, a resist film (not shown) is deposited on the hard mask material and patterned with the footprint and location of each of fin-shaped region 502, 504. In one example, RIE is used to form the fin hard masks, and therefore the resist film comprises a resist material such as hydrogen silsesquioxane (HSQ) patterned using electron beam (e-beam) lithography and transferred to a carbon-based resist.

As described in greater detail herein below, portions of fin-shaped regions 502, 504 formed by nanowire Si layers 104, 302, once released from sacrificial SiGe layers 202, 402, will form nanowire channels of the semiconductor device. Because the fin etch is being performed before the dummy gate/replacement gate steps (described in greater detail later herein), the semiconductor device fabrication processes described herein may be referred to as a fin first process. Additionally, because the nanowire channels (e.g., portions of nanowire Si layers 202, 402) formed in fin-shaped regions 502, 504 will be released from the sacrificial layers 104, 302 after the dummy gate/replacement gate steps, the semiconductor device fabrication process described herein may also be referred to as a wire last process. Each sacrificial SiGe layer 104, 302, following the fin etch, is thinner than each nanowire Si layer 202, 402. Additional details of suitable GAA nanowire FET structures fabricated according to replacement gate, fin-first, wire last fabrication techniques are disclosed in U.S. Pat. No. 8,809,313, which is assigned to the assigned of the present disclosure, and which is incorporated by reference herein in its entirety.

FIG. 6A depicts a cross-sectional view of the semiconductor device after a next fabrication stage. FIG. 6B depicts a cross-sectional view of the semiconductor device shown in FIG. 6A, taken along line 6B-6B, and FIG. 6C depicts a cross-sectional view of the semiconductor device shown in FIG. 6A, taken along line 6C-6C. As shown in FIGS. 6A, 6B, and 6C, a dummy gate 602 is formed over fin-shaped regions 502, 504 using an HK deposition process. As also shown in FIGS. 6A, 6B and 6C, a hard mask (HM) 604 is deposited over dummy gate 602. As also shown in FIGS. 6A, 6B and 6C, offset spacers 606 are formed along the sidewalls of dummy gate 602, as shown. Offset spacers 606 may be formed using a spacer pull down formation process. Offset spacers 606 may also be formed using a sidewall image transfer (SIT) spacer formation process, which includes spacer material deposition followed by directional RIE of the deposited spacer material. The nanowire portions of fin-shaped regions 502, 504 that are surrounded by dummy gate 602 will form the nanowire channel regions of the semiconductor device.

FIG. 7A depicts a cross-sectional view of the semiconductor device after a next fabrication stage. FIG. 7B depicts a cross-sectional view of the semiconductor device shown in FIG. 7A, taken along line 7B-7B, and FIG. 7C depicts a cross-sectional view of the semiconductor device shown in FIG. 7A, taken along line 7C-7C. As shown in FIGS. 7A, 7B and 7C, the exposed portions of fin-shaped regions 502, 504 are recessed in the source drain region using a silicon RIE process. The recessed fin-shaped regions 502, 504 can be controlled such that the full channel width of each layer 104, 202, 302, 402 is exposed on a surface of offset spacers 606.

FIG. 8A depicts a cross-sectional view of the semiconductor device after a next fabrication stage. FIG. 8B depicts a cross-sectional view of the semiconductor device shown in FIG. 8A, taken along line 8B-8B, and FIG. 8C depicts a cross-sectional view of the semiconductor device shown in FIG. 8A, taken along line 8C-8C. As shown in FIGS. 8A, 8B and 8C, sacrificial SiGe layers 104, 302 are pulled back from underneath offset spacer 606 using a hydrogen chloride (HCL) gas isotropic etch process.

FIG. 9A depicts a cross-sectional view of the semiconductor device after a next fabrication stage. FIG. 9B depicts a cross-sectional view of the semiconductor device shown in FIG. 9A, taken along line 9B-9B, and FIG. 9C depicts a cross-sectional view of the semiconductor device shown in FIG. 9A, taken along line 9C-9C. As shown in FIGS. 9A, 9B and 9C, in accordance with one or more embodiments of the present disclosure, diffusion blocks 902 are formed to fill the space formed in sacrificial SiGe layers 104, 302. Diffusion blocks 902 may be formed conformally by CVD, or by monolayer doping (MLD) of nitride followed by spacer RIE. Diffusion blocks 902 are positioned such that subsequent etching processes that remove sacrificial layers of the channel region during device fabrication do not also attack the source and drain regions 1002, 1004 (shown in FIGS. 10A, 10B and 10C) of the semiconductor device. Diffusion blocks 902 may be formed from a nitride containing material (e.g., silicon nitride (SiN)), which prevents excess gauging during subsequent RIE processes (e.g., sacrificial layer removal) that are applied during the semiconductor device fabrication process. Although diffusion blocks 902 shown in FIGS. 9A, 9B and 9C are formed from a nitride containing material, they may be formed from any material for which subsequent device fabrication operations are not very selective. Selectivity, as used in the present disclosure, refers to the tendency of a process operation to impact a particular material. One example of low selectivity is a relatively slow etch rate. One example of a higher or greater selectivity is a relatively faster etch rate. For the disclosed embodiments, a material for diffusion blocks 902 is selected based on a selectivity of subsequent device fabrication operations for the selected material being below a predetermined threshold.

FIG. 10A depicts a three-dimensional view of the semiconductor device after a next fabrication stage. FIG. 10B depicts a cross-sectional view of the semiconductor device shown in FIG. 10A, taken along line 10B-10B, and FIG. 10C depicts a cross-sectional view of the semiconductor device shown in FIG. 10A, taken along line 10C-10C. As shown in FIGS. 10A, 10B and 10C, raised source/drain (SD) regions 1002, 1004 are formed using an epitaxial layer growth process on the ends of exposed nanowire Si layers 202, 402. In-situ doping (ISD) is applied (e.g., by ion implantation) to form doped S/D regions 1002, 1004, thereby creating the necessary junctions of the semiconductor device. Virtually all semiconductor transistors are based on the formation of junctions. Junctions are capable of both blocking current and allowing it to flow, depending on an applied bias. Junctions are typically formed by placing two semiconductor regions with opposite polarities into contact with one another. The most common junction is the p-n junction, which consists of a contact between a p-type piece of silicon, rich in holes, and an n-type piece of silicon, rich in electrons. N-type and p-type FETs are formed by implanting different types of dopants to selected regions of the device to form the necessary junction(s). N-type devices may be formed by implanting arsenic (As) or phosphorous (P), and p-type devices may be formed by implanting boron (B).

FIG. 11 depicts a cross-sectional view of the semiconductor device shown in FIG. 10A, taken along line 11-11. As previously noted, S/D regions 1002, 1004 are in-situ doped (e.g., by ion implantation) to form extension regions 1102 having extension junctions 1104 within nanowire Si layers 202, 402. Extension regions 1102 and extension junctions 1104 extend under offset spacers 606, and the regions of nanowire Si layers 202, 402 under gate dummy gate 602 remains undoped. The doping of extension regions 1102 can be performed by implanting nanowire Si layers 202, 402 with ions. Extension junctions 1104 reduce the R_(ext) of the nanowire FET device when turned on by a gate bias voltage, and also form a conducting path between S/D regions 1002, 1004 and channel regions formed by nanowire Si layers 202, 402.

FIG. 12 depicts the nanowire FET device shown in FIG. 11 after a near-final fabrication stage, wherein the dummy gate 602 and sacrificial SiGe layers 104, 302 have been removed by a known etching process, e.g., RIE or chemical oxide removal (COR). In a gate-late fabrication process, the removed dummy gate structure 602 (shown in FIGS. 6A to 11) is thereafter replaced with a metal gate (not shown) as known in the art. Dummy gate 602 can be removed by an etching process, e.g., RIE or COR, to form a trench. A dielectric material and one or more gate metals (not shown) can then be deposited within the trench. For example, an HK dielectric material, e.g., hafnium based material, can be deposited to form a gate dielectric. A metal liner, e.g., a work-function metal, and a gate metal can then be deposited on the dielectric material to complete the gate formation. In one or more embodiments, the metal liner can be, for example, TiN or TaN, and the gate metal can be aluminum or tungsten.

FIG. 13 is a flow diagram illustrating a methodology 1300 according to one or more embodiments. At block 1302 alternating sacrificial layers and nanowire layers are formed. Block 1304 patterns the alternating sacrificial layers and nanowire layers to form fin-shaped stacks. Block 1306 forms a dummy gate and spacers over portions of the fin-shaped stacks. The portions of the nanowire layers underneath the gate will form the channel region of the nanowire FET device. Block 1308 recesses the fin-shaped stacks in areas not covered by the gate and the spacers. Block 1310 removes sidewall portions of the sacrificial layers by selectively etching the sacrificial layers from the outside wall of the spacer to the dummy gate. Block 1312 backfills the removed sidewall portions with diffusion blocks (e.g., blocks of selective SiN). Block 1314 grows source/drain regions such that the diffusion blocks are between the sacrificial layers and the source/drain regions. Growing the source/drain regions may include in-situ doping to form the necessary junctions for either n-type or p-type nanowire FET devices, including extension junctions in the nanowire layers at the interface between the nanowire layers and the source/drain regions. Block 1316 removes the sacrificial layers using a sacrificial layer removal process such as an etching process. The diffusion blocks prevent the sacrificial layer etching process from laterally etching the source/drain regions.

Thus, it can be seen from the forgoing detailed description and accompanying illustrations that embodiments of the present disclosure provide structures and methodologies for providing a nanowire FET device having improved junction design, reduced series resistance and improved source to drain sheet resistance. In one or more embodiments, the semiconductor device fabrication methodology includes processes to remove and release sacrificial layers from nanowire layers that will form the channel region of the device. A diffusion block is locally formed between the sacrificial layers and the source and drain regions of the device. The diffusion block is positioned such that processes that remove the sacrificial layers of the channel region during device fabrication do not also attack the source and drain regions of the device. The diffusion block may be formed from nitride, which prevents excess gauging during certain reactive ion etch (RIE) processes that may be applied during the sacrificial layer removal process of the overall device fabrication process. The diffusion block may be formed from any material for which subsequent device fabrication operations are not very selective. Selectivity, as used in the present disclosure, refers to the tendency of a process operation to impact a particular material. One example of low selectivity is a relatively slow etch rate. One example of a higher or greater selectivity is a relatively faster etch rate. For the disclosed embodiments, a material for the diffusion block is selected based on a selectivity of subsequent device fabrication operations for the selected material being below a predetermined threshold.

The methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated. 

What is claimed is:
 1. A nanowire field effect transistor (FET) comprising: a nanowire channel layer having a first end region; a diffusion block formed under the first end region of the nanowire channel layer; and a source region or a drain region positioned adjacent the diffusion block and the first end region of the nanowire channel; wherein the diffusion block comprises a material having a selectivity to predetermined fabrication operations of the FET; wherein the selectivity of the diffusion block prevents the predetermined fabrication operations of the FET from removing portions of the source region or the drain region.
 2. The nanowire FET of claim 1, wherein the predetermined fabrication operations of the FET comprise wet processes.
 3. The nanowire FET of claim 2, wherein a selectivity of the wet process to the diffusion block is below a predetermined threshold.
 4. The nanowire FET of claim 2, wherein the wet process comprises an etch.
 5. The nanowire FET of claim 4, wherein the etch comprises a reactive ion etch.
 6. The nanowire FET of claim 5, wherein the reactive ion etch causes an etch rate of the diffusion block that is below a predetermined threshold.
 7. The nanowire FET of claim 1 further comprising a plurality of nanowire channel layers.
 8. The nanowire FET of claim 1 further comprising: a gate region around the nanowire channel layer; wherein the gate region controls a flow of current through the nanowire channel layer.
 9. The nanowire FET of claim 1, wherein the source region or the drain region include dopants that form at least one junction.
 10. The nanowire FET of claim 9, wherein the first end region of the nanowire channel layer comprises an extension junction of the nanowire layer.
 11. A nanowire field effect transistor (FET) comprising: a nanowire channel layer having a first end region and a second end region; a first diffusion block formed under the first end region of the nanowire channel layer; a second diffusion block formed under the second end region of the nanowire channel layer and a source region or a drain region positioned adjacent the first diffusion block, the second diffusion block, the first end region of the nanowire channel, and the second end region of the nanowire channel layer; wherein the first and second diffusion blocks comprise a material having a selectivity to predetermined fabrication operations of the FET; wherein the selectivity of the first and second diffusion blocks prevents the predetermined fabrication operations of the FET from removing portions of the source region or the drain region.
 12. The nanowire FET of claim 11, wherein the predetermined fabrication operations of the FET comprise wet processes.
 13. The nanowire FET of claim 12, wherein a selectivity of the wet processes to the first and second diffusion blocks is below a predetermined threshold.
 14. The nanowire FET of claim 12, wherein the wet processes comprise an etch.
 15. The nanowire FET of claim 14, wherein the etch comprises a reactive ion etch.
 16. The nanowire FET of claim 15, wherein the reactive ion etch causes an etch rate of the first and second diffusion blocks that is below a predetermined threshold.
 17. The nanowire FET of claim 11 further comprising a plurality of nanowire channel layers.
 18. The nanowire FET of claim 11 further comprising: a gate region around the nanowire channel layer; wherein the gate region controls a flow of current through the nanowire channel layer.
 19. The nanowire FET of claim 11, wherein the source region or the drain region include dopants that form at least one junction.
 20. The nanowire FET of claim 19, wherein: the first end region of the nanowire channel layer comprises a first extension junction of the nanowire channel layer; and the second end region of the nanowire channel layer comprises a second extension junction of the nanowire channel layer. 